Towards fast error correction for quantum key distribution

The implementation of the decoy state protocol in Quantum Key Distribution (QKD) can improve the raw key rate of the system. This improvement, when coupled with expected advances in the available technology, particularly in single photon detectors, promise significantly increased raw key rates in the near future. As such, improvements to the classical error correction used in a QKD system are required in order to keep up with the potential increase in key rates. [1] Low-Density Parity-Check (LDPC) codes have recently been shown to provide very desirable properties for error correction under belief propagation decoding. They offer both near Shannon limit performance and the potential for highly efficient decoding algorithms. In particular, the decoding algorithm is parallelizable, allowing for fast hardware implementations. [2] Efficient implementations in hardware, whether it is a custom Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA), require that computations are performed using fixed-point arithmetic. The performance of a LDPC code is simulated at different error rates around 3% while using various bit lengths to represent the data during decoding and the results are compared with double precision floating-point calculations. It is shown that for an irregular LDPC matrix of size 4000x1200 with check node degree 20 and message node degree between 2 and 8, excellent results are obtained using 20-bit fixed-point arithmetic. References: [1] D. Pearson, Proc. 7th Int. Conf. Quantum Communication, Measurement and Computing, 734, 299-302 (2004); [2] B. Levine et al., Proc. IEEE Symp. Field-Programmable Custom Computing Machines, 217-226 (2000).