Towards GHz clocked QKD for telecommunication networks

Quantum key distribution (QKD) is the only technique currently known that provides cryptographic key exchange over an untrusted public communication channel with information theoretic security [1]. Here, we present the current status of our QKD system. In the system, a DFB laser diode is used to generator 500ps-width laser pulses, which is strongly attenuated to single-photon level per pulse as qubits. With a polarization modulator based on a 10GHz LiNbO3 phase modulator, these qubits are modulated to four polarization states that are needed in the BB84 protocol. To remove the threat of eavesdropping based on photon-number-splitting attacks, the decoy protocol is performed by using an intensity modulator [2]. The intensity modulator and the polarization modulator are temperature insensitive and spectrum independent. The latter property is important to a high-speed QKD system. The system also allows sending of classical framing information via sequences of strong laser pulses (classical bits), inspired by the Ethernet protocol. These classical bits has been planned to compensate polarization drift of the fiber link, synchronize the sender's and receiver's electronic equipments, identify source and destination which provides routing information on a network and exchange public information that is required in quantum cryptography protocols. Moreover, by encoding classical bits, a standard could be created in order to adapt and integrate QKD systems from different vendors into one network. Both, the classical bits and the qubits are transferred along one single 11km long fiber link between laboratories located at University of Calgary (UofC) and Southern Alberta Institute of Technology (SAIT). Home-made high-speed circuits based on FPGAs are used to control the key distribution process and acquire the raw key bits. At the same time, fast error correction is achieved by performing low density parity check (LDPC) on FPGAs, for which, only one-way communication is required, high-speed parallel hardware implementations are possible and most importantly the efficiency relative to the Shannon limit is optimized [3]. [1] N. Gisin, G. Ribordy, W. Tittel and H. Zbinden, Rev. Mod. Phys, vol. 74, 145 (2002). [2] B. Huttner, N. Imoto, N. Gisin and T. Mor., Phys. Rev A, 51, 1863 (1995). [3] D.J.C. MacKay and R.M. Neal, Electron. Lett, 33 (1997).